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-- Implemetacion de un registro de memoria de 8 bits
-- Amilcar J., Erazo P.
----------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

--Entidad registro de 12 bits

entity pipeline_instruction is
    port (
        INPUT_i       : in  std_logic_vector (11 downto 0);
        CLK_i         : in  std_logic;
        INSTR_FETCH_i : in  std_logic;
        OUTPUT_REG0_o : out std_logic_vector (11 downto 0);
        OUTPUT_o      : out std_logic_vector (11 downto 0));
end pipeline_instruction;

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architecture behavioral of pipeline_instruction is

	component reg12bits
		port (
			D_i   : in  std_logic_vector (11 downto 0);
			CLK_i : in  std_logic;
            E_i   : in  std_logic;
			Q_o   : out std_logic_vector (11 downto 0) );
	end component;

	signal w : std_logic_vector(11 downto 0);

	begin
		U0 : reg12bits port map ( INPUT_i, CLK_i, INSTR_FETCH_i, w);
		U1 : reg12bits port map ( w , CLK_i, INSTR_FETCH_i, OUTPUT_o);

        OUTPUT_REG0_o <= w;

end behavioral;

-- vim: tabstop=4 : shiftwidth=4 : expandtab
